SPRD DWC3 glue logic

This file documents the parameters for the dwc3 driver.
This driver controls the glue logic used to configure the dwc3 core on
ROC1 based platforms.

Required properties:
 - compatible	: must be "sprd,roc1-dwc3", "sprd,orca-dwc3"
 - reg		: glue logic base address and USB syscfg ctrl register offset

 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
   with 'reg' property

 - ranges	: allows valid 1:1 translation between child's address space and
		  parent's address space

 - clocks	: a list of phandle + clock-specifier pairs, one of each
		  entry on clock-names

 - clock-names	: Should contain "core_clk", "ref_clk", "susp_clk".
		  "ipa_usb_ref" and "ipa_usb_ref_source" are optional properties.

 - power-domains : A phandle pointed to the corresponding power domain

Sub-nodes:
The dwc3 core should be added as subnode to SPRD DWC3 glue as shown in the
example below. The DT binding details of dwc3 can be found in:
Documentation/devicetree/bindings/usb/dwc3.txt

NB: The dr_mode property described in [1] is NOT optional for this driver, as the default value
is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-sprd are either "host"
or "device".

[1] Documentation/devicetree/bindings/usb/generic.txt

Example:
usb3: usb3@20f00000 {
	compatible = "sprd,roc1-dwc3";
	reg = <0 0x20f00000 0 0x100000>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	clocks = <&ipa_gate CLK_IPA_USB_EB>,
		<&ipa_gate CLK_IPA_USB_SUSPEND_EB>,
		<&ipa_gate CLK_IPA_USB_REF_EB>;
		<&ipa_clk CLK_USB_REF>,
		<&g12_pll CLK_TWPLL_24M>;
	clock-names = "core_clk", "ref_clk", "susp_clk",
		"ipa_usb_ref", "ipa_usb_ref_source";
	power-domains = <&pd_ipa_sys>;

	dwc3@20f00000 {
		compatible = "synopsys,dwc3";
		reg = <0 0x20f00000 0 0x100000>;
		interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "irq";
		usb-phy = <&ssphy>, <&ssphy>;
		usb-pam = <&pamu3>;
		phy_type = "utmi_wide";
		dr_mode = "peripheral";
		snps,usb3-u1u2-disable;
		snps,dis_u3_susphy_quirk;
		snps,dis_u2_susphy_quirk;
		snps,overlap_check_quirk;
		snps,ep_out_aligned_size_quirk;
		snps,disconnect_event_quirk;
	};
};

